A study on current handling capability of dual gate MOS thyristor (DGMOS)

This paper describes the experimental results of new Dual Gate MOS Thyristor (DGMOS), which can be fabricated with the same process technology as IGBT. In order to investigate the mechanism of turn-off failure in a large chip, which occurs lower current density compared with smaller chip, 9.0/spl times/7.2 mm 600 V-DGMOS with internal gate interconnection have been evaluated. The inhomogenious current distribution is the major reason of turn-off failure. In order to realize higher current handling capability, the formation of lower resistance gate interconnection is one of the key technologies as well as developing the new cell structure which has higher latch-up immunity.