Architecture simplications for an improved performance RAKE receiver

A new architecture for a RAKE receiver using n samples per chip period is studied in order to find the best trade-off between the achievable performance and the complexity of a receiver for direct-sequence code division multiple access system for mobile radio. The architecture of this n-oversampled RAKE receiver is described as well as a means of reducing complexity based on a proper selection of the coefficients of the estimated channel impulse response. Simulation results on bit-error-rate (BER) at the output of the 4-oversampled RAKE as a function of E/sub s//N/sub o/ are presented for an indoor channel for binary phase shift keying (BPSK) and quadrature phase shift keying (QPSK). For comparison purposes, simulation results for two more conventional RAKE receivers using one sample per chip period and selecting either arbitrarily or dynamically the sampling instant are also given. For the 4-oversampled RAKE, significant reduction of the complexity with respect to the case of the processing of all paths is achieved.