ESD design for deep submicron SOI technology [NMOS transistor]

This paper establishes the critical ESD design issues for a partially depleted 0.35 /spl mu/m SOI process. Through device analysis we show for the first time that the gate bias of an NMOS during ESD plays a critical role in reducing channel heating and in achieving good protection levels for both positive and negative stress polarities. With an optimum design window, we demonstrate greater than /spl plusmn/2 kV ESD performance with no additional process steps.