FPGA Implementation of Wavelet Transform Based on Lifting Scheme

This paper presents FPGA implementation of 2D discrete wavelet transform to compress the images for retrieval and storage. The whole design is written in VHDL using Xilinx ISE and ISE Simulator is used for Simulation. The motivation is to use reconfigurable hardware for implementing high performance block. Essentially the same piece of silicon can be reprogrammed to achieve different functionalities. We use in place computation to reduce hardware requirement. The design can be used for both lossy and lossless image compression.