Architecture-aware design of a decimation filter based on a dual wordlength multiply-accumulate unit

In this work we present the design and implementation of a decimation filter for an audio range DeltaSigma-modulator. The architecture is based on a dual wordlength multiply-accumulate (MAC) unit to handle the reduced wordlength of the input. Each stage is composed of FIR filters which are mapped to the MAC unit. The design trade-offs and decisions for co-design of architecture and filters are discussed.