Easy to fill sloped vias for interconnects applications improved control of silicon tapered etch profile

The first part of this paper aims to illustrate the possibility to control the shape of the top of a tapered silicon via using an SF₆/O₂ chemistry with high etch rate (~14 mum/min). This etch has been performed using an ICP machine, customized for this type of etch. Usually, for such a tapered etch process, a local bowed sidewall profile undercuts the mask at the top of the via. By removing this local bow, the aim is to facilitate the use of such tapered profile for through silicon via (TSV) interconnects, as used for CMOS applications or MEMS packaging in mass production today. The second part of this paper relates to the study of some trends obtained by varying process parameters such as pressure or platen power.