Reliability of fine-pitch flip-chip packages

A new low-cost flip-chip technology that leverages the existing fine pitch flip-chip technologies is discussed. For decades, the C4 process has served as the main interconnect method in the flip-chip package. However with bump pitches shrinking, the solder bump based C4 process is facing challenges in terms of reducing pitch and underfill process. At the same time, increasing challenges for flip-chip are seen by the movement toward lead-free solder bumps and low-k dielectric layers. This paper provides an overview of Tessera muPILRtrade flip-chip technology incorporating a 150um pitch bump array and the simulations and study conducted on reliability of Tessera muPILR flip-chip package. This study explores the effect of various design parameters on package warpage. Solder fatigue life prediction was performed and solder bump reliability was compared for Tessera flip-chip technology and standard flip-chip solder joints using Modified Anand solder material properties and Darveaux fatigue life prediction theory. Initial experimental reliability results are also presented which highlight the reliability/feasibility of Tessera developmental muPILR flip-chip package design for 150um bump pitch. Further more, fracture mechanics approach was applied, and energy release rates were obtained in order to check reliability of low-k dielectric layer.