Applying Verification Collaterals for Accurate Power Estimation

Accurate and efficient power estimation at higher-levels of abstraction is becoming increasingly important. However, tools and methodologies are lacking for such a task. In this paper, we present a methodology for accurate power estimation at high-level by reusing pre-existing verification or validation resources in the design flow. This novel methodology enables architectural exploration and design optimization through a framework that exploits the abstraction aspect of high-level designs and the availability aspect of well-established tool flows for RTL designs. Thereby, utilizing the best from both worlds (high-level and low-level) to bring forth a fast and accurate enough solution to a well-known problem in the design of low power embedded systems and SoCs. In this paper, the focus is on how to apply our approach on a deign of reasonable complexity. We present the case study of a power state machine controller that is a critical component of most power-aware embedded systems. The approach uses verification collaterals such as test content, assertions, etc., which are normally built during the verification process of a high-level design to enable power profiling and estimation. The presented methodology is specific to a high-level synthesis and power estimation framework.