Layout-driven factorization and fitting for cellular-architecture FPGAs

The characteristic feature of the new cellular-architecture FPGA is a local connectivity between the adjacent cells. This paper presents nontraditional approaches to layout synthesis of the cellular-architecture FPGA. In the first approach, a multi-level network, in the form of DAG, is mapped to the target architecture using a simulated evolution. The parameters controlling the simulated evolution are defined such that the routing structure of the target architecture is considered during placement. In the second approach, a restricted multilevel network (RML), obtained by the architecture driven factorization of two-level representation of logic functions, is mapped to the target architecture. This method produces rectangular-shaped, locally-connected solutions which are the best structures for two-dimensional cellular arrays such as fine grain FPGAs.