Mapping of symmetric and partially-symmetric functions to the CA-type FPGAs

This paper presents a new approach to technology mapping of symmetric and partially-symmetric logic functions to Fine-Grain Cellular-Architecture FPGAs. The method is based on Ordered Binary Decision Diagrams (BDDs). Properties of symmetric functions are used to generate Reduced Ordered BDDs for symmetric and partially symmetric functions that can be easily mapped to the rectangular, locally connected arrays of CA-type FPGAs. The mapping method is presented for the existing FPGA architecture, and routing domain modification is suggested for improved mapping. Examples of FPGA layouts are given.