CRC-based techniques for combined burst synchronization and error detection in TDMA PCS systems

The TDMA architecture of the PACS system for personal communications services (PCS) is novel in that, while the downlink includes a synchronization field (SYC) to aid timing acquisition, the uplink does not. Instead, PACS uses coset coding at the transmitter to aid uplink synchronization. Bellcore has recommended a two-step CRC-based algorithm for joint burst synchronization and slot error detection. In this paper, we study an alternate method in which successive error-detection syndromes are serially computed using a slight modification of the customary polynomial-division shift register. Effectively eliminating one of the two steps in the Bellcore algorithm, this method produces a hardware implementation of lower complexity and less processing delay. Furthermore, unlike the Bellcore method, it is compatible with the use of shortened cyclic codes.