Effective BIST for crosstalk faults in interconnects

The paper is devoted to a test-per-clock method of an at-speed testing of crosstalk faults in long interconnects between cores in systems-on-a-Chip. A linear feedback shift register (LFSR) composed of 2n flip-flops and implementing primitive polynomial was used as a test pattern generator (TPG) for an interconnect network comprised of n nets. In our approach every second output of the LFSR is connected to the interconnect network under test (INUT). Simulation-based experiments were carried out to verify effectiveness of vector sequences produced by the proposed TPG in detection of crosstalk faults provoked at victim net by simultaneous occurrence of rising (falling) edges 01(10) at k aggressor lines. Crosstalk faults causing occurrence of a positive (negative) glitch at a victim line having constant value 00(11) as well as the ones that make the edge delayed with an opposite direction 10(01) at a victim line were taken into consideration. Experimental results demonstrated that for n e {8,12,16,20,24,28,32} and k<