Giga-bit scale DRAM cell with new simple Ru/(Ba,Sr)TiO/sub 3//Ru stacked capacitors using X-ray lithography

We have fabricated experimental memory cell arrays with a unit cell size of 0.29 /spl mu/m/sup 2/ (0.38 /spl mu/m/spl times/0.76 /spl mu/m). The layout was designed for a half-pitch 8F/sup 2/ cell with 0.14-/spl mu/m process technology, which is promising for 1-gigabit DRAMs and beyond. We developed three advanced technologies for this fabrication. Firstly, synchrotron radiation (SR) X-ray lithography was used to replicate ultra-fine patterns instead of optical lithography. Secondly, we introduced a simple stacked capacitor composed of a metal-organic chemical vapor deposition (MOCVD) grown (Ba,Sr)TiO/sub 3/ (BST) high-dielectric-constant film sandwiched by Ru-metal electrodes. Thirdly, we developed advanced etching techniques for the fine pattern fabrication using improved ECR discharged plasmas, which give less microloading effects.