A 9b 14µW 0.06mm2 PPM ADC in 90nm digital CMOS

As CMOS dimensions scale down, time-domain resolution of digital signals improves but the voltage resolution of analog signals degrades [1]. In this paper, we introduce an ADC architecture based on Pulse Position Modulation (PPM), which relies more on time resolution than on amplitude resolution. In PPM (Fig. 9.4.1(a)), a continuous-time comparator compares the input signal with a voltage ramp. The time interval between the ramp starting point, which is synchronous with the reference clock, and the instant the input signal crosses the ramp (i.e. [t
1
, t
2
, t
3
, Ω] in Fig. 9.4.1(a)) is measured by a 2-step time-to-digital converter. Assuming the ramp slope is constant, we can calculate the input-signal amplitude from the measured time vector.