Systematic design of encoder and decoder networks with applications to high-speed signal processing

The authors consider alternative implementations of multiple threshold circuits and stacked signal adders as code converters between the binary-weighted and unary-weighted data representations. The proposed approach leads to the use of only two logic switches instead of comparators, and there is no need to explicitly form the threshold level values. For the set of threshold levels {0,...,2/sup k/-1} in the decoder, the number of switches is N/sub s/=2/sup k+1/-2k-2. The delay of the circuit is T=(k-1)/spl tau//sub s/, where /spl tau//sub s/ is the switching time of the logic elements. The encoder network has similar characteristics. The proposed circuits can be used in nonlinear digital filters, distributed calculations, and flash A/D converters.