Domain Coverage Metric for SoC Validation

The importance of System-On-Chip (SoC) validation continues to grow with the increase of design size. How to measure the completeness and quality of validation approach? An innovative domain coverage metric is proposed in this paper. Domain methodology is based on a geometrical analysis of the domain boundary and takes advantage of the fact that point on or near the boundary is most sensitive to domain errors. The coverage tool has been implemented using Verilog procedural interface (VPI) and has been applied to validation of SoC under design. Results show that the domain coverage can detect many design faults that statement and path coverage can not.