BIST Approach for testing Embedded Memory Blocks in System-on-Chips

This paper presents a built-in self-test (BIST) approach to test embedded memory blocks in configurable system-on-chips (SoCs). The idea of this paper is to develop BIST architecture and BIST configurations for testing embedded memory blocks in Xilinx Virtexl-4 series SoCs by using an embedded FPGA core. The proposed approach tests RAMs operating in all of different sizes both in single-port and dual- port modes. The paper also has developed a parameterized VerilogHDL code which is portable and can be used to test embedded memories with minimal changes in any configurable SoCs.