Periodic loop structure for combining power FETs

N-y circuit level power combiner for FETs that achieves a 1/N impedance transformation ratio and can be implemented in a single layer microstrip technology is proposed. The inverse relationship of each FET with N gives low impedance, which is efficient for operating power FETs from a low supply voltage. The feasible values of transmission line characteristic impedance are used, and the combiner circuit is completely planar and therefore can be realised with a single layer microstrip technology.