Testable design of microcontrollers using a RISC approach

This paper deals with the CPU design for microcontrollers as a RISC architecture using design for testability techniques. The instruction set is defined, the processor logic design is performed and the on chip structure for test vectors generation, using the minimum area, is presented. We used the results of algorithmic information theory to balance the complexity of the self test machine with that of the test sequence, so that the area is minimised.