The design and technology requirements of a 9-channel RS485 transceiver for ultra-SCSI applications

The design aspects of a 9-channel ultra-SCSI transceiver chip are discussed including improvements to speed, power consumption and die size over a previous generation chip, Discussion of the enabling linear BiCMOS technology and an ESD strategy, critical to the function of this class of chip, are presented. Finally, the results of prototype silicon are reviewed.