Charge recycling differential logic for low-power application

Energy efficiency has become one of the most important concerns in VLSI design. Conventional dynamic circuit techniques, which are preferred for high-speed operation, are inefficient as far as power consumption is concerned. Charge-recycling differential logic (CRDL) improves power efficiency by using some of the already-used charge for precharge. It has the benefit of improved noise margin due to inherently static operation.