Abstract:
This paper describes a hybrid latch-flipflop (HLFF) timing methodology aimed at a substantial reduction in latch latency and clock load. A common principle is employed to...Show MoreMetadata
Abstract:
This paper describes a hybrid latch-flipflop (HLFF) timing methodology aimed at a substantial reduction in latch latency and clock load. A common principle is employed to derive consistent latching structures for static logic, dynamic domino and self-resetting logic.
Published in: 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC
Date of Conference: 10-10 February 1996
Date Added to IEEE Xplore: 06 August 2002
Print ISBN:0-7803-3136-2
Print ISSN: 0193-6530
