Graceful capacity degradation for ultra-large hierarchical memory structures

A design for implementing graceful capacity degradation in large capacity hierarchical memories is presented. Previous research provided a means for testing and repairing blocks of memory. In the presence of an excessive number of faults, blocks may not be fully repairable. When coupled with the test and repair structure, this scheme will allow the memory capacity to degrade gracefully, i.e., the memory will still operate with a lower total capacity. The scheme was implemented and simulated using a 0.8 /spl mu/m CMOS process technology. Initial results show relatively small area overhead with a repair time of 2.5 ns best case.