Power analysis of a programmable DSP for architecture/program optimization

Power consumption has become one of the primary metrics in CMOS LSI design. A high level power estimation model will be indispensable to evaluate architectures and programming styles for performance and power consumption optimization. A model was proposed in which a constant energy was used for every module but data dependency was not taken into account. The purpose of this paper is to quantify the module break down and the data dependency of the power consumption and to find a key for high level power estimation. We analyzed power consumption of a 24 bit fixed point DSP, HX24, which we developed previously. We have found that the buses do not consume as much power as we originally expected while the data operation modules consume much power and the data dependency caused about 30% variation in worst case chip power. This is the first paper that describes how large the data dependency of data operation is and how low the bus power consumption is in a DSP of an extended Harvard architecture.