A 60 ns 3.3 V 16 Mb DRAM

The authors describe a single 3.3-V, 16-Mb DRAM (dynamic RAM) fabricated in a 0.5- mu m, twin-well CMOS technology and packaged in a 400-mil small-outline J-leaded package. The design features are an array architecture based on the twisted-bit-line (TBL) technique and a multipurpose register (MPR) enabling an effective line mode test (LMT), copy write, and high-speed cache access capability. Under typical conditions at V/sub cc/=3.3 V, a row-address-strobe access time of 60 ns was obtained. Features of the RAM are summarized.<>