A digital video signal processor for color image sensors

The authors describe signal processor (DSP) for CCD (charge-coupled-device) cameras using a specified color filter array pattern. A block diagram of the DSP chip is shown. The chip has been designed and fabricated in a 2- mu m single-poly double-metal CMOS process. Eight scan-test registers were used at selected points in the processing chain to enable the entire chip to be tested, including ROMs and line delays, with 16 k vectors. The chip is functional at a maximum clock rate of 14.3 MHz. An image processed by the device is shown. The data path is designed with simple ripple-carry adders and dynamic registers. The on-chip programmable delay lines and 14.3-MHz clock-rate allow the chip to accommodate sensors for up to 768 active pixels, making it suitable for NTSC, CCIR 601 and PAL video standards.<>