An experimental 4 Mb CMOS EEPROM with a NAND structured cell

A 5-V-only CMOS 512 K*8 EEPROM (electrically erasable and programmable read-only memory), which achieves 10/sup 4/ cycle endurance using a NAND-structured cell, is discussed. The main features are a programming technique appropriate to the NAND structured cell and a dynamic sense amplifier. The NAND structured cell arranges 8 bits in series, sandwiched between two select transistors. The first transistor ensures selectivity; the second prevents the current from passing during programming operation. The current cell has one select transistor per bit. However, the NAND structure has only two select transistors per 8 bits; therefore it has only 1/4 select transistor and 1/16 contact hole per bit. Thus, the NAND structure can realize a smaller cell area than that of the current cell. For high-speed programming, a page mode is adopted. In read operation, address transition detection circuitry is used to precharge the bit lines and reset the read control circuitry. A summary of design characteristics is presented.<>