Design of high-performance 32-bit embedded processor

This paper describes the implementation of high-performance 32-bit embedded processor, Core-A. Core-A processor has unique instruction set architecture(ISA) in the form of Reduced Instruction Set Computer(RISC). Especially, Core-A processor has several unique features for code density and DSP applications. Since Core-A processor is described using Verilog HDL, it can be customized for a given application and synthesized for an ASIC or FPGA target. Also, software tool chain including compiler, assembler, linker, and debugger has been developed for Core-A processor. Core-A processor with separate cache is implemented using a 0.18um 1P4M CMOS process and the real-time edge detection system is designed with Altera FPGA for evaluation system.