Area-efficent power clamp circuit using gate-coupled structure for Smart Power ICs

Area-efficient ESD (Electro Static Discharge) power clamp using gate-coupled structure for Smart Power technology is proposed. The use of Big-FET parasitic Capacitance results in the reduction of the total size of the circuit when compared to the Darlington scheme and RC triggered circuits. The performance of the proposed ESD power clamp was successfully verified in a 0.35um 60V BCD (Bipolar CMOS DMOS) process by TLP (Transmission Line Pulse) measurements.