Capturing all branches of any one-port characteristic in piecewise-linear resistive circuits

An algorithm to capture all the unicursal branches of any one-port characteristic in piecewise-linear (PWL) resistive circuits is described. The heart of this algorithm is based on the so-called polyhedral augmented circuits: they are constructed by replacing each PWL element by a suitable polyhedral element and by connecting a norator to the one-port. The structure of the algorithm is based on a genealogical tree, whose nodes represent specific polyhedral augmented circuits. All branches of the PWL one-port characteristic can be captured by checking the solution domains of these circuits. From the numerical point of view, the investigation of the nodes requires the execution of related Linear Programming (LP) problems, one for each node, However, the similar structure of their tableaux allows the reduction of the overall CPU time.