Analysis of performance and reliability trade-off in dummy pattern design for 32-nm technology

Deep sub-micron technologies employ dummy metal fills in the interconnect layouts with adequate pre-CMP pattern density distribution to achieve post-CMP planarization. Dummy metal placement has a significant impact on interconnect parasitic capacitance and it also alters the mechanical stresses in the interconnect structure. The combined effects of dummy placement on the parasitic capacitance and the mechanical stresses are examined in this study. The impact of the dummy placement is found to be strongly correlated with the dummy fill pattern. Some patterns studied here result in improved interconnect parasitic parameters but lead to a deterioration in the local stress fields that are of reliability concern. Therefore, the dummy placement must be designed such that both performance and reliability are taken into consideration.