Fault Modeling and Analysis for Bridging Defects in a Synchronizer

This paper presents fault modeling and analysis for bridging defects in a synchronizer that is implemented by two D flip-flops. Bridging defects are injected into any two nodes of the syncronizer, and HSPICE is used to perform circuit analysis. The defects are exhaustively injected and simulated to find all possible faults that might occur in the synchronizer. The results obtained can be used to develop methods for testing the interfacing circuits between different clock domains.