Efficient tests and DFT for RAM address decoder delay faults

This paper presents an analysis, at the electrical level, of address decoder faults caused by resistive opens within (a) dynamic address decoders and (b) static address decoders, which have special circuits that deactivate them at fixed moment. Efficient algorithms are proposed to cover the targeted faults. DFT circuit, to facilitate the BIST implementation of the proposed tests, is also provided. Furthermore, the limitations of the current/existing approaches in detecting delay faults are addressed.