Design and Implementation for High Speed LDPC Decoder with Layered Decoding

This paper presents a layered decoding algorithm for LDPC code and analyzes the advantages and challenge for high speed implementation. Simulation result indicates that layered decoding algorithm converge two times faster than traditional decoding algorithm. A new code construction scheme aimed to design high speed LDPC decoder with layered decoding algorithm is put forward. This code construction method helps to increase the parallel degree of decoder by suffering with little performance loss. Using the layered decoding algorithm and code construction scheme, a length 2304, rate 1/2 LDPC decoder which can achieve about 768 Mbps information throughput has been implemented on FPGA platform.