A 13GHz Low Power Multi-Modulus Divider Implemented in 0.13μm SiGe Technology

This paper presents a generic architecture for programmable multi-modulus dividers (MMD) for low- power and high-speed frequency synthesis applications. The proposed architecture uses cascaded divide by 2/3 cells in a ripple fashion with the last cell constructed using a P/P+1 dual modulus prescaler. Using a P/P+1 divider instead of a conventional 2/3 cell saves power and die area. The P/P+1 division ratio can be used to adjust MMD's minimum division ratio and the required division range. This approach provides an optimized architecture with minimum current consumption, the smallest area and minimum number of control bits for designing MMDs with a unit step increment. An MMD prototype was implemented in a 0.13 mum SiGe technology and occupies a core area of .88 times .10 mm2. The 13GHz MMD RFIC contains four 2/3 cells followed by an 8/9 cell. It can be programmed from 128 to 159 and consumes 11 mA under a 2.2V power supply, which corresponds to 59.2% power reduction compared to the prior art MMD implementations.