Impact of poly field plate dimension towards LDMOS performance

Rapid increasing demand towards high voltage MOSFETs device integrated in low voltage CMOS analog and digital circuits for automobile and power management application has driven the development of 0.18um high voltage lateral diffused MOSFET (LDMOS) which capable to have 80V breakdown voltage. During designing this high voltage LDMOS, it is observed that the device performance is very dependent towards the device geometry particularly poly overlap length on STI. Thus, in this paper, the effects of poly overlap length on STI plate for high voltage LDNMOS have been studied extensively during the off-state condition.