Design of I/Q demodulator for W-CDMA

The design of an Inphase-Quadrature (I/Q) demodulator with low current consumption is described. The I/Q demodulator was designed for wideband code division multiple access (W-CDMA) communication system. SiGe 0.35 mum BiCMOS technology with f_T = 45 GHz, f_max = 60 GHz and noise figure = 0.8 dB at 2 GHz was used for the design. A top-down and bottom-up approach was used in designing the I/Q demodulator. CMOS devices were primarily used in the biasing circuits for power consumption reduction while SiGe bipolar devices were used in signal path circuits. The design contained 2 mixers, a local oscillator (LO) divider, negative resistance circuit, buffer amplifiers and bias/control circuits. The I/Q demodulator circuits were then layout and had gone through the post-layout simulation to check performance with the parasitic elements which were introduced from the layout. A design prototype was measured and was found to be agreed with the simulation results. The prototype worked in the region of 190 MHz input frequency and 0-35 MHz output frequency. The prototype had also met the specifications for the W-CDMA hand phone receiver. It achieves EVM of 2.9%. It is also achieved gain ripple of 0.12 dB, gain mismatch of 0.1 dB and phase mismatch of 1.25deg. Finally, the design which is consisted of mixers, frequency dividers, VCO buffer amplifiers and bias/control circuits consumes 4 mA with 3 V power supply.