Optimum quad band DCO in DS method for WCDMA transmitter in 90nm CMOS

We try to optimize the fully integrated phase path for a 3G polar transmitter in deep sub micron CMOS. It includes a single quad band digitally controlled oscillator (DCO)[1] providing modulation capability to handle the wide bandwidth of the WCDMA phase (frequency) data with using a nonlinearity cancellation technique, DS [3] compensator network and a switched inverter divider with interpolating up/down sampling. The complete chip, with integrated LDOs, power consumption of 20 mA at 2.5 V.