Hybrid clock network for altera structure ASIC devices

Clock performance becomes a challenge in Structure ASIC world when system performance requirement keep increasing and logic density grows rapidly. In general, clock performance is evaluated through the clock skew and the clock integrity. The difficulty in ensuring minimum clock skew while maintaining clock integrity becomes more challenging when the device size grows and clock frequency increases. In this paper, we are introducing a new clock network structure for Altera Structure ASIC device (Hardcopy II), namely Hybrid Clock Network[1]. The Hybrid clock network provides better performance on clock skew and clock integrity compared to previous generation Altera Structure ASIC device (Stratix HC) and FPGA.