Efficient algorithms for analyzing and synthesizing fault-tolerant datapaths

We address optimization problems arising in the synthesis of application specific integrated circuits (ASICs) that recover from transient faults via a rollback and retry approach. In this approach, each segment of a computation is duplicated and the results are compared using comparators. If the compared values are unequal, the computation is rolled back to the beginning of the segment (rollback point) and retried. Previous work in this area has generally been of an experimental nature focusing on heuristic approaches. We examine these problems from an algorithmic perspective. Several comparison and rollback strategies for reducing hardware costs and the delay caused by a transient fault have been previously proposed. For various combinations of these comparison and rollback strategies, we present efficient algorithms to analyze a given design to determine the maximum delay that can be caused by a transient fault of a given duration. These algorithms are based on formal characterizations of when a transient fault can cause a maximum delay for each combination of comparison and rollback strategies. We have also developed an efficient algorithm for designing fault-tolerant datapaths under hardware and delay constraints.