High speed architectural implementation of CORDIC algorithm

Advances in the VLSI technology have provided designers with significant impetus for porting algorithm into architecture. In this paper, we propose an architecture with low latency for the implementation of CORDIC algorithm in rotation mode suited for parallel and pipelined operation. In our proposed architecture, redundant radix-4 arithmetic is employed to reduce iteration delay and halve the number of iterations. The iteration delay is further reduced by predicting the directions of all microrotations without performing rotation.