Stepped Die Packaging

With the increase in memory needed by consumer, higher capacity memory is in greater demand. But before the next higher density memory die is available, memory chips are normally stacked to achieve the required density. The current package structures of a stacked die package is either using thick epoxy pillow embedding the bond-wires or have a dummy silicon die or polymer tape as a spacer between the stacking units. This paper focuses on the development of a novel, spacer-less stacked multi-die packaging through the use of stepped die. The package does not require silicon or polymer materials as spacer to facilitate same die stacking because each of this stepped die has an indent cut at periphery, providing the necessary clearance for all bond-wires. Critical processing challenges are investigated, including 1) dicing of stepped die; 2) die attach of stepped die; 3) cantilever wire bonding; and 4) molding pile of stacked stepped die. Live samples have been built to demonstrate the feasibility of such packaging approach and the test yield associated with stepped silicon die. In addition, the reliability of this new live stacked multi-die assembly is also being evaluated. Samples meet MST L2, T/C "B" 1000 cycles and HAST 96 hrs requirement.