Contribution of Interface States and Oxide Traps to the Negative Bias Temperature Instability of High-$k$ pMOSFETs

Negative bias temperature instability (NBTI) in MOSFETs with high-dielectric-constant (
k
) gate dielectrics has been investigated using a novel pulse NBTI measurement technique. This technique enabled the separation of the contribution of interface states (
N

_it
) from that of oxide traps (
N

_ot
) to NBTI behavior by varying the measurement time (
t

_m
) and the delay time (
t

_R
). The technique was demonstrated on devices fabricated with different postdeposition annealing (PDA) conditions. It was found that, regardless of the PDA condition, the
N

_ot
in high-
k
dielectric was more responsible for the NBTI behavior than the
N

_it
, but the contribution of
N

_it
to NBTI increased as the stress continued because the generation rate of
N

_it
was higher than that of
N

_ot
.