Yield modeling using the SPIROS redundancy planner

The performance of the rule-based SPIROS system in modeling the yield of VLSI systems incorporating redundancy is discussed. SPIROS has been used in the design of four experimental VLSI circuits. Yield projections for these chips match the experimental data to within 11%, and are within 5% for one closely modeled system. The design of these systems is presented as case studies, and it is shown where the ability to model alternatives at a high level changed the choice of architecture for two of these systems.<>