HBHT (High Bandwidth High Throughput) waveform porting demonstration using GRA-compatible Hardware Abstraction Layer (HAL)

The HBHT waveforms stress technologies and typically require specialized HW and SW design techniques to meet Size Weight and Power (SWaP) and performance requirements. Because of the high data rates and complex algorithms required by these waveforms, high speed processing elements (i.e. Field Programmable Gate Arrays-FPGAs) must be employed in the modem implementation. However, the Government Reference Architecture (GRA) requires the use of a common programmable modem to host multiple waveforms. The GRA also requires use of a signal processing Hardware Abstraction Layer (HAL) to facilitate 3^rd party waveform porting and waveform re-use across programs. L-3 CSW and Raytheon recently collaborated to prove the GRA concepts of 3^rd party waveform porting, use of a common programmable modem to host multiple HBHT waveforms, and use of a signal processing HAL to facilitate waveform re-use and efficient waveform porting. The demonstration included successful 3^rd party waveform porting of XDR, 165-A, and CDL, with data rates up to 100psilas of Mbps.