Impedance Matching Techniques in 65nm CMOS Power Amplifiers for 2.4GHz 802.11n WLAN

This paper describes the design of two power amplifiers (PA) for WLAN 802.11n fabricated in 65 nm CMOS technology. Both PAs utilize 3.3V thick-gate oxide (5.2 nm) transistors and employ a two-stage differential structure, but the input and interstage matching networks are realized differently. The first PA uses LC matching networks for matching, while the second PA uses on-chip transformers. The impedance matching techniques applied for the matching networks will be described. EVM, output power levels, and spectral masks are obtained for a 72.2 Mbit/s, 64-QAM, 802.11n, OFDM signal.