Design and implementation of co-design toolset for tcore processor

Application-specific instruction processors (ASIP) tailored for the requirements are often at the center of today’s embedded systems. Therefore, considerable effort has been spent on constructing tools that assist in co-designing ASIP. It is desirable that such design toolsets support an automated design flow from application source code down to synthesizable processor description and optimized machine code. In this paper, we will describe such a toolset for Tcore processor which is derived Transport Triggered Architecture (TTA). We have addressed some of the pressing shortcomings found in existing toolsets, especially the design of compiler. Finally, we present a satisfied result of an image contrast enhancement algorithm implemented using Tcore processor under many kinds of configuration through the toolset.