An 8B/10B encoder with a modified coding table

This paper presents a design of 8B/10B encoder with a modified coding table. The proposed encoder has been designed based on a reduced coding table with a modified disparity control block. After being synthesized using CMOS 0.18μm process, the proposed encoder shows the operating frequency of 343 MHz and occupies the chip area of 1886 μm² with 189 logic gates. It consumes 2.74mW power. Compared to conventional approaches, the operating frequency is improved by 25.6% and chip area is decreased to 43%.