The Realization of FFT Algorithm Based on FPGA Co-Processor

The fast Fourier transform (FFT)is a computationally intensive digital signal processing(DSP)function widely used in applications such as imaging ,software-defined radio, wireless communication, instrumentation and machine inspection. Historically, this has been a relatively difficult function to implement optimally in hardware leading many software designers to use digital signal processors in soft implementations. Unfortunately , because of the functionpsilas computationally intensive nature, such an approach typically requires multiple digital signal processors within the system to support the processing requirements. This is costly (from a device and board real-estate perspective) as well as power-intensive. FPGA co-processors have become an extremely cost-effective means of off-loading computationally intensive algorithms to improve overall system performance. For example ,an FFT FPGA co-processor implementation that utilizes dedicated hardware multiplier resources can cost effectively achieve ASIC-like performance while reducing development time ,cost ,and risks. This paper will describe two FFT implementation approaches, one implemented as an FPGA co-processor and the other using only an external digital signal processor. It will then examine the advantages and disadvantages of these approaches from performance cost, power consumption , and ease-of-implementation perspectives.