Process-design co-optimization for FPGA

Advancement of field programmable gate array (FPGA) faces many challenges. Among the major ones are power management and high speed transceiver I/O demands. To overcome the challenges, process-design co-optimization is required. With co-optimization of process, circuit, and architecture, 45% static power reduction is achieved for a 40 nm FPGA design. With optimized analog devices, high data rate (8.5 Gbps) transceivers are produced using a 40 nm digital process.